The present invention generally relates to semiconductor devices, and more particularly relates to a device and method for determining the line edge roughness effect of individual features on device performance.
Lithography in semiconductor processing relates generally to the process of transferring patterns which correspond to desired circuit components onto one or more thin films which overlie a substrate. One important step within the field of lithography involves optical tools and methods for transferring the patterns to the films which overlie the semiconductor wafer. Patterns are transferred to a film by imaging various circuit patterns onto a photoresist layer which overlies the film on the wafer. This imaging process is often referred to as xe2x80x9cexposingxe2x80x9d the photoresist layer. The benefit of the exposure process and subsequent processing allows for the generation of the desired patterns onto the film on the semiconductor wafer, as illustrated in prior art FIGS. 1a-1f. 
Prior art FIG. 1a illustrates a photoresist layer 10 deposited by, for example, spin-coating, on a thin film 11 such as, for example, silicon dioxide (SiO2) which overlies a substrate 12 such as silicon. The photoresist layer 10 is then selectively exposed to radiation 13 (e.g., ultraviolet (UV) light) via a photomask 14 (hereinafter referred to as a xe2x80x9cmaskxe2x80x9d) to generate one or more exposed regions 16 in the photoresist layer 10, as illustrated in prior art FIG. 1b. Depending on the type of photoresist material utilized for the photoresist layer 10, the exposed regions 16 become soluble or insoluble in a specific solvent which is subsequently applied across the wafer (this solvent is often referred to as a developer).
The exposed regions 16 are made either soluble or insoluble in the developer. When the exposed regions 16 are made soluble, a positive image of the mask 14 is produced in the photoresist layer 10, as illustrated in prior art FIG. 1c, and the photoresist material is therefore referred to as a xe2x80x9cpositive photoresistxe2x80x9d. The exposed underlying areas 18 in the film 11 may then be subjected to further processing (e.g., etching) to thereby transfer the desired pattern from the mask 14 to the film 11, as illustrated in prior art FIG. 1d (wherein the photoresist layer 10 has been removed). Conversely, when the exposed regions 16 are mode insoluble, a negative image of the mask 14 is produced in the photoresist 10 layer, as illustrated in prior art FIG. 1e, and the photoresist material is therefore referred to as a xe2x80x9cnegative photoresistxe2x80x9d. In a similar manner, the exposed underlying areas 20 in the film 11 may then be subjected to further processing (e.g., etching) to thereby transfer the desired pattern from the mask 14 to the film 11, as illustrated in prior art FIG. 1f. 
The transfer of patterns to the photoresist layer 10 as discussed above involves the use of optical aligners. Optical aligners are machines which contain a variety of subsystems that work together to form the imaging function. Such optical aligners include: (1) an illumination source which provides the optical energy (UV light in the above example) for transforming the photoresist via exposure, (2) an optical subsystem that focuses the circuit patterns onto the photoresist surface and allows for controlled exposure times, and (3) and a movable stage that holds the wafer being exposed.
Historically, three primary methods have been used to optically transfer a mask pattern to a photoresist covered film. These methods are: contact printing, proximity printing and projection printing and are illustrated in simplified form in prior art FIGS. 2a-2d, respectively. Contact printing 100, as illustrated in prior art FIG. 2a, was the earliest method used to produce patterns. Contact printing 100 involves a light source 112, an optical system 114, a mask 116 and a photoresist layer 118 overlying a thin film 119 (not shown) which, in turn, overlies a semiconductor wafer 120. The mask 116, which contains the desired circuit patterns for transfer to the photoresist layer 118, is positioned (aligned) relative to any existing patterns that already existed on the wafer 120. The mask 116 is then clamped down to the photoresist layer 118, thereby making physical contact with the photoresist layer 118, and exposed with ultraviolet (UV) light from the light source 112. This method provides for an excellent image transfer and good resolution (i.e., good minimum linewidth spacing).
Contact printing, however, suffers from the direct contact made between the mask 116 and the photoresist layer 118. The repeated contact made between the mask 116 and the photoresist layer 118 in the process results in defects generated in the mask 116 which are then reflected in the transfer made on subsequently processed wafers. To prevent this problem, the masks 116 must be disadvantageously inspected and cleaned regularly. In addition, small particles may be caught between the mask 116 and the photoresist layer 118 when affixing the two elements, thereby preventing the desired direct contact between the mask 116 and the photoresist layer 118. This particulate contamination results in reduced resolution in the area local to the foreign particle. Consequently, contact printing is not common in VLSI semiconductor manufacturing.
Proximity printing 122, as illustrated in prior art FIG. 2b, involves placing the mask 116 near the wafer 120 (which is covered with the photoresist 118) during exposure, however, the mask 116 and the wafer 120 do not make contact. By introducing a gap 124 between the mask 116 and the wafer 120, the defect problem of contact printing is substantially avoided. Unfortunately, as the gap 124 increases, the resolution of the proximity printing system 122 rapidly deteriorates. For example, a 10 xcexcm gap with a 400 nm exposure (the wavelength of the light source 112) results in a minimum resolution of about 3 xcexcm. In addition, proximity printing 122 requires extremely flat masks 116 and wafers 120 in order to prevent gap variations spatially about the wafer 120. Since many VLSI semiconductor circuits today require features of 0.25 xcexcm or less, proximity printing 122 is not considered adequate for many VLSI semiconductor manufacturing operations.
Projection printing is a generic term that encompasses various pattern transfer techniques. These techniques, for example, include: (a) projection scanning systems, (b) reduction (e.g., 4xc3x97or 10xc3x97) step-and-repeat projection systems and (c) reduction step-and-scan systems. In each system, lens elements or mirrors are used to focus the mask image on the wafer surface (containing the photoresist).
Projection scanning systems (often called scanning projection aligners), use a reflective spherical mirror (reflective optics) to project an image onto the wafer surface, as illustrated, for example, in prior art FIG. 2c. The system 126 includes a primary mirror 128 and a secondary mirror 129 which are arranged with the mask 116 and the wafer 120 to image the mask pattern onto the photoresist layer 118 which overlies the film 119 on the wafer 120 (the photoresist layer 118 and the thin film 119 are not shown in FIG. 2c for simplicity). A narrow arc of radiation is imaged from the mask 116 to the wafer 120 with light that travels an optical path that reflects the light multiple times. The mask 116 and the wafer 120 are scanned through the arc of radiation by means of a continuous scanning mechanism (not shown). The scanning technique minimizes mirror distortions and aberrations by keeping the imaging illumination in the xe2x80x9csweet spotxe2x80x9d of the imaging system 128 and 129.
Reduction step-and-repeat systems 130 (also called reduction steppers) use refractive optics (as opposed to reflective optics in the system 126 of prior art FIG. 2c) to project the mask image onto the photoresist layer 118 which overlies the film 119 on the wafer 120, as illustrated, for example, in prior art FIG. 2d. The reduction stepper 130 includes a mirror 132, a light source 134, a filter 136, a condenser lens system 138, a reticle 140, a reduction lens system 142 and the wafer 120. The mirror 132 behaves as a collecting optics system to direct as much of the light from the light source 134 (e.g., a mercury-vapor lamp) to the wafer 120. The filter 136 is used to limit the light exposure wavelengths to the specified frequencies and bandwidth. The condenser system 138 focuses the radiation through the reticle 140 and to the reduction lens system to thereby focus a xe2x80x9cmaskedxe2x80x9d radiation exposure onto a limited portion of the wafer 120, namely onto a single semiconductor die 144.
Since it is complex and expensive to produce a lens capable of projecting a mask pattern of an entire 150 mm or 200 mm wafer, the refractive system 130, as illustrated in prior art FIG. 2d, projects an image only onto a portion of the wafer 120 corresponding to an individual semiconductor die 144. This image is then stepped and repeated across the wafer 120 in order to transfer the pattern to the entire wafer (and thus the name xe2x80x9csteppersxe2x80x9d ). Consequently, the size of the wafer is no longer a consideration for the system optics.
The reduction stepper system 130 thus uses the reticle 140 instead of a mask. Reticles are similar to masks, but differ in that a mask contains a pattern for transfer to the entire wafer in one exposure while a reticle contains a pattern image for a single or several semiconductor die that must be stepped and repeated across the wafer 120 in order to expose the entire wafer substrate. Today, however, the terms xe2x80x9cmaskxe2x80x9d and xe2x80x9creticlexe2x80x9d are used interchangeably. Current reduction stepper systems such as the system 130 utilize reticles that contain a pattern that is an enlargement of the desired image on the wafer 120. Consequently, the reticle pattern is reduced when projected onto the wafer 120 during exposure (and thus the name xe2x80x9creduction stepperxe2x80x9d).
One advantage of stepper technology over the full wafer scanning type technology is higher image resolution (i.e., smaller minimum linewidths). In addition, stepping each die on the wafer 20 allows compensation for wafer distortion. Further still, reduction steppers provide good overlay accuracy. Steppers do, however, exhibit reduced throughput (number of wafers/hour) and require precision control of the mechanical stage (not shown) which holds the wafer 120. The advantages of reduction steppers, however, presently outweigh their disadvantages and thereby make reduction steppers quite popular in the manufacture of VLSI semiconductors with minimum linewidths less than 1 xcexcm.
The goal of a high performance lithography system is to provide a high resolution, repeatable system which reduces the linewidth of features produced thereby. In addition to providing small, repeatable linewidths, it is also desirable to provide linewidth uniformity across the image field. That is, it is desirable to provide a lithography system in which a designer can expect the linewidth of various features across the image field to fall within a predetermined range of a nominal, target value (i.e., Xxc2x1xcex94X). Prior art FIG. 3 illustrates a plan view of a processed semiconductor wafer 200 having a plurality of die 202 thereon, wherein one of the die 204 is amplified to show a plurality of features thereon which were formed by the lithography system of interest. For a step and repeat type system, the image field typically encompasses the entire semiconductor die 204. For example, as illustrated in prior art FIG. 4, which illustrates a plurality of similar features 206 across the die 204 of FIG. 3, if the nominal linewidth of a feature is X, system linewidth uniformity would ensure that such features would have a linewidth within xc2x1xcex94X of the target value (e.g., about 5%) at any location on the die 204. As lithography systems and processes continue to improve, the average linewidth variation across the image field continues to decrease, thus indicating greater linewidth uniformity.
It is important for lithography developers to ascertain the average linewidth variation (xcex94XAVG) across the image field in order to properly characterize and develop new lithography components and processes (e.g., exposure processes, mask materials, photoresists, imaging systems, etc.) to further enhance linewidth uniformity. As linewidths and the average linewidth variation continues to shrink, however, distilling average linewidth variations due to the lithography system from other phenomena becomes increasingly difficult. One such phenomena is called line edge roughness (LER) and refers to the variations on the sidewalls of features.
LER occurs in patterned features and is caused primarily by a corresponding LER within an overlying photoresist which is used as a mask for the patterning of the features. LER in photoresist masks is caused by various factors, including LER on the chrome patterns which reside on the reticle, the image contrast of the system used in generating the photomask pattern, the plasma etch with which the photoresist pattern is formed, the photoresist material properties and the photoresist processing scheme. The LER in the overlying photoresist mask is then transferred into the underlying film (e.g., metal, polysilicon, etc.). In addition to LER in the photoresist mask, the plasma etch used in patterning the underlying film further contributes to the LER of the patterned feature.
As feature sizes continue to shrink, the contribution of LER to the entire feature linewidth variation becomes more pronounced and thus it is important to separate or distill the LER from average linewidth variations caused by the lithography system and process. With such information, each component which makes up the entire linewidth variation (i.e., LER and the lithography system) can be separately characterized and processes can be developed to reduce each component. Prior art FIG. 5 is a fragmentary perspective view which illustrates a portion of a feature 210 which represents the variation from the average linewidth (i.e., xcex94Xi). The feature 210 has a nonuniformity 212 at a lateral edge 214 which is attributable to LER. Since the feature 210 which represents the linewidth variation from the nominal linewidth is substantially large (e.g., a poor quality lithography process having large linewidth variations), however, the nonuniformity 212 is relatively small with respect thereto and thus may be effectively ignored. In contrast, as illustrated in phantom with the dotted line 220 in prior art FIG. 5, as the linewidth variations become smaller (i.e., xcex94Xixe2x80x2) the nonuniformity 212 is more pronounced with respect to the entire linewidth variation and must be taken into account. More particularly, it is important for the lithography developer to separate LER from average linewidth variations due to the lithography system and process so that subsequent process development can properly focus on each component of linewidth variation separately.
In addition, as device features continue to shrink, LER impacts the process control, for example, causing the channel lengths of various transistors to vary from one another beyond a maximum threshold and thus undesirably resulting in device performance variations. Unfortunately, although prior art methods exist for measuring the LER associated with a given feature (e.g., via an atomic force microscope (AFM) or a scanning electron microscope (SEM)), presently there is no effective way of coupling the LER to the resulting device performance repeatability in order to provide minimum device feature size specifications or quantify whether a particular process provides a sufficiently low LER to meet a given device performance repeatability specification.
The present invention relates to a structure and related method for determining a line edge roughness (LER) of a patterned feature using device characteristics of multiple devices, wherein the patterned feature is a common component within the devices. The present invention also relates to a structure and method of determining a preferred minimum device dimension based on a determination of the impact of LER on the device performance repeatability.
According to one aspect of the present invention, a structure for determining the line edge roughness of a patterned feature is disclosed. The structure includes a plurality of transistors having the patterned feature as a common gate electrode for the transistors. The transistors are activated using the gate electrode and the conduction current within each of the transistors is a function of the width of the gate electrode immediately overlying each channel region, respectively. The conduction currents of the transistors are measured and used to separate line edge roughness from linewidth variation components due to other types of lithography variables.
The distilling of line edge roughness from other factors is achieved, for example, by calculating an average and a standard deviation of the conduction currents. The average conduction current of the transistors is attributable to the average gate width and can be used to deduce the average linewidth variation of the patterned feature which is associated with other, non-LER process factors. Similarly, the standard deviation of the conduction currents is attributable to the amount of variation of the patterned feature width about its average and is used to deduce the line edge roughness of the patterned feature (i.e., the gate).
According to another aspect of the present invention, a method of separating line edge roughness from other linewidth variation components includes the forming of a plurality of transistors having a common gate electrode which serves as the patterned feature of interest. Each of the transistors are activated to place the transistors in a conducting mode and the conduction current of each transistor is then measured. Using the measured conduction currents, the line edge roughness of the patterned feature is separated from the other linewidth variation components. According to one exemplary aspect of the present invention, the separation is achieved by calculating the average and the standard deviation of the conduction currents, wherein the average current is associated with the linewidth variation attributable to other, non-LER lithography process factors while the standard deviation is associated with the degree of linewidth variation of the gate about its average width and thus is attributable to the line edge roughness of the feature.
According to still another aspect of the present invention, a method of determining a minimum device feature size (e.g., transistor width) based on a predetermined device performance criteria (e.g., repeatability) is disclosed. The method includes forming a plurality of test structures, wherein each of the test structures include a plurality of transistors having a patterned feature (having an LER) as a common gate electrode for the transistors. The transistors within each test structure preferably have the same width, and each of the test structures have transistor widths that differ from each other. The transistors of each test structure are activated using their gate electrode and the conduction current for each of the transistors is then measured. Because each test structure employs transistors having differing widths, the standard deviation of the conduction currents (due to the LER) for each test structure will also differ and reflect the impact of the gate electrode LER on transistor performance repeatability. Based on a predetermined performance repeatability criteria applied to the standard deviation data, one of the test structures is selected. The transistor width of the selected test structure represents the minimum transistor width which may be utilized while maintaining performance variations due to LER that are below a predetermined level. Consequently, the present invention provides a method of establishing a processing design specification which minimizes the impact of LER on device performance repeatability.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.